1. Field of the Invention
The present invention relates to a fabrication technology for semiconductor devices, and, more particularly, to a dry etching technique for an interlayer insulating film in a process for fabricating a semiconductor device.
2. Description of the Prior Art
In a process for fabricating a semiconductor device, such as VLSI or ULSI, to electrically interconnect transistors formed on the major surface of a semiconductor wafer (hereinafter simply called xe2x80x9cwaferxe2x80x9d) and metal interconnection lines, minute contact holes are formed in an interlayer insulating film (thin film essentially consisting of silicon oxide; hereinafter called xe2x80x9coxide filmxe2x80x9d) formed on an upper portion of the transistor structure and between the interconnection lines by a dry etching technique using a plasma, and a semiconductor or metal is filled in the contact holes. Then, the transistors are electrically interconnected, and so are the metal interconnection lines both via the semiconductor or metal.
Dry etching is a technique which selectively etches a target film (interlayer insulating film) by transforming an etching gas fed into a vacuum chamber into a plasma with high frequency power externally applied and accurately reacting reactive radicals or ions produced in the plasma on the wafer.
As the miniaturization of semiconductor devices and the speed improvement progress, it becomes important to reduce the contact resistance between the base semiconductor layer in the contact hole formed by dry etching or the base interconnection lines and the metal filled in the contact hole.
The following are known techniques of reducing the contact resistance in a contact hole (through hole) formed by dry etching or preventing wiring corrosion at the bottom of a contact hole.
(1) Japanese Patent Laid-Open No. 286115/1992 (prior art 1):
The prior art 1 discloses a technique of eliminating a foreign matter from a contact hole and reducing the contact resistance by placing a semiconductor device in an atmosphere containing heated hydrogen, an atmosphere containing a hydrogen plasma or an atmosphere containing a hydrogen plasma and chlorine plasma after etching, thereby removing a deposit from the contact hole.
(2) Japanese Patent Laid-Open No. 251294/1999 (prior art 2):
The prior art 2 discloses a technique of forming a low-resistance contact on the premise that the base contains a metal silicide. According to the prior art 2, when a photo-resist mask after formation of a contact hole is eliminated by ashing, a nitrogen-based active species is used to prevent oxidation of the metal silicide.
(3) Japanese Patent Laid-Open No. 145282/1999 (prior art 3):
The prior art 3 discloses a technique of removing a deposition film containing a metal, such as Al, sticking on the sidewall of a through hole without causing corrosion of the Al wiring or the like at the bottom of the through hole. According to the prior art 3, after a deposit in the through hole is removed by the BCl3 which is a reducing gas, resist ashing is carried out with a plasma containing H and O.
The fabrication of semiconductor devices, such as VLSI and ULSI, requires the improvement of the throughput. A multichamber processing system mentioned below is known as fabrication equipment to improve the throughput.
(4) The specification of U.S. Pat. No. 5,292,393 (prior art 4):
The prior art 4 discloses a multichamber processing system which comprises etch, deposition, sputtering and RTA (Rapid Thermal Annealing) chambers.
In fabricating a ULSI device based on design rules after the 0.1-xcexcm scale, the following points should be satisfied more.
(1) To set the aspect ratio (depth of contact hole/diameter of contact hole) to 15 or greater.
(2) To carry out high selectivity contact-hole etching with a bowing-free etched shape.
(3) To reduce the contact resistance in a contact hole.
xe2x80x9cBowingxe2x80x9d is disclosed in Negishi et al., xe2x80x9cHigh-Aspect-Ratio Contact hole etching in UHF-ECR plasmaxe2x80x9d, pp 31-36, 2000 Dry Process Symposium.
To fulfill the requirements, the present inventors studied techniques of reducing the contact resistance in a contact hole. The following discusses the reviews.
Contact holes were processed using a UHF-ECR plasma etching system. For example, an interlayer insulating film was selectively etched by feeding a fluorocarbon gas, such as CF4, CHF3, C2F6, C3F6O, C4F8, C5F8 or C4F6, into a vacuum chamber, forming a plasma in a pressure range of 0.5 Pa to 10 Pa and accelerating the ion energy incident to a wafer from 0.5 kV to 2.5 kV.
To form contact holes with a high aspect ratio, it is necessary to suppress etch stop and improve the etching rate that affects the throughput. Therefore, etching was carried out while keeping the ion energy relatively high from the beginning of etching to the end thereof.
There is an issue of nonuniformity of etching rate over the wafer surface. It is necessary to prevent some of contact holes from being unformed in the wafer surface due to the nonuniform etching rate. To meet the requirement, overetching was performed with the etching time being about 120 to 130% with respect to the depth of contact holes. The xe2x80x9cnonuniformity of etching ratexe2x80x9d means a difference in etching rate between the center portion of the wafer and the peripheral portion thereof.
Overetching causes the surfaces of active regions or interconnection layers at the bottoms of some of the contact holes to be exposed to ion bombardment with high ion energy for about 20% to 30% more than the adequate etching time. That is, the ion bombardment may damage the active region or its surface. Specifically, the active region is the source-drain region of an MOS transistor which is formed in a single-crystalline silicon substrate to serve as an MOS element.
Further, dissociation of the fluorocarbon gas causes C radicals or O radicals generated in the plasma to be implanted in the active region by the incident ions. As a result, a high resistivity layer containing SiC or SiOx is formed several nanometers deep in the active region. This high resistivity layer is a factor which increases the contact resistance. The increased contact resistance hinders the improvement of the speeds of semiconductor devices such as ULSI.
One way to suppress an increase in contact resistance originated from the high resistivity layer is to generate a plasma with a gas mixture of a gas having a large fluoride content, such as CF4, and an Ar gas or O2 gas after formation of a contact hole and remove the high resistivity layer with relatively low ion energy of 500 V or below.
As the gas contain a large amount of C (carbon) or O (oxygen), however, the high resistivity layer would remain on the surface in the contact hole. This requires that the high resistivity layer be removed by wet processing using a solution which contain a hydrofluoric solution.
Because isotropic etching progresses in the wet processing, the insulating film on the sidewall of the contact hole is also etched out. This brings about a new problem that the finished sizes would become wider than the designed sizes. In the fabrication process for DRAMs (Dynamic Random Access Memories) of 1 Gbits or larger, particularly, this problem becomes one of factors that hinder the miniaturization.
Accordingly, it is an object of the invention to provide a process for fabricating semiconductor devices which achieves large scale integration and improves the speed of the semiconductor devices.
It is another object of the invention to improve the throughput in the fabrication of semiconductor devices.
The above and other objects of the invention and the features thereof will be readily apparent from the following detailed description, taken in conjunction with the accompanying drawings.